In SOI technology, a thin layer of silicon (typically featuring a thickness of a few nanometers) is separated from a semiconductor substrate by a relatively thick electrically insulating layer (typically featuring a thickness of a few tens of nanometers).
Integrated circuits in SOI technology offer a number of advantages compared to traditional “bulk” technology for CMOS (Complementary Metal Oxide Semiconductor) integrated circuits. SOI integrated circuits typically provide a lower power consumption for a same performance level. Such circuits also feature a reduced stray capacitance, allowing an increase of commutation speeds. Furthermore, the latch-up phenomena encountered in bulk technology can be mitigated. Such circuits are therefore particularly adapted to SoC (System on Chip) or MEMS (Micro electro-mechanical systems) applications. SOI circuits also are less sensitive to ionizing radiations, making them more reliable than bulk-technology circuits in applications where said radiations may induce operating problems, such as aerospace applications. SOI integrated circuits can include memory components such as SRAM (Static Random Access Memory), or logic gates.
Much research has been conducted on reducing the static power consumption of logic gates, while increasing their commutation speed. Some integrated circuits combine both logic gates with low power consumption, and logic gates with high commutation speed. In order to integrate two such logic gates on a same integrated circuit, it is known to lower the threshold voltage (typically noted VT or Vth) of some transistors belonging to the high-speed logic gates, and to lower the threshold voltage of some other transistors of the low-consumption logic gates. In bulk technology, threshold voltage modulation is implemented by differentiating the doping level of the semiconductor canal of these transistors. However, FDSOI (Fully Depleted Silicon On Insulator) transistors have, by design, a depleted canal, featuring a low doping level (typically 1015 cm−3). Due to this low doping level, it is not possible to modulate the threshold voltage of transistors with the method used in bulk technology. Some studies have proposed integrating different gate materials in otherwise identical transistors, in order to obtain differing threshold voltages. However, implementing this solution is technically challenging and economically prohibitive.
In order to obtain different threshold voltages for transistors in FDSOI technology, it is also known to include an electrically biased ground plane (also named back plane, or back gate), located between a thin electrically insulating oxide layer, and the silicon substrate. This technology is often known as UTBOX (for Ultra-Thin Buried OXide layer). By adjusting the doping levels of, and the electrical bias applied to these ground planes, it is therefore possible to define several ranges of threshold voltages for said transistors. For example, it is possible to define low-threshold voltage transistors (LVT), high-threshold voltage transistors (HVT) and medium or standard threshold voltage transistors (SVT).
Some publications have proposed modifying the structure of FDSOI integrated circuits. A practical problem, as with any such technological evolution, is that the software used to design said circuits may end up being incompatible with the modified circuits and may require substantive development.
As large-scale integrated circuits have become too complex to be designed by hand, circuit designers typically rely on computer-assisted design (CAD) software tools, also known as electronic design automation (EDA). For current technology nodes, numerous parameters must be taken into account in order to avoid a malfunction or a destruction of the circuits.
Many EDA tools use a functional specification as input. This functional specification describes the desired behaviour of the circuit, as well as non-functional design constraints (such as, for example, circuit surface, cost, and power consumption). ESD tools output a computer file describing a circuit at a physical level (usually in the GDSII file format or, more recently, the OASIS file format). This computer file defines layouts used to manufacture masks. Such masks are then used in semiconductor foundries, during photolithography steps of the integrated circuit fabrication process.
Standard EDA design flow typically comprises several steps.
First, starting with a user-specified functional specification of the circuit, the concept and the global architecture of the circuit is modelled at a high-level of abstraction. The performance of this modelled circuit is then validated. Typically, at this step, the circuit is modelled using a description language such as Verilog, VHDL, SPICE or other.
Then, during floorplanning step, the position of power connections and portions of the circuit is roughly mapped.
Then, a logic synthesis of the circuit is performed. The circuit is modelled at a register-transfer level (RTL). More specifically, the implementation of the circuit is modelled as a combination of several sequential elements as well as logic combinations between the respective inputs and outputs of the sequential elements and the primary inputs and outputs of the integrated circuit. This modelling provides a network, formed essentially of logic gates and hardware registers. This modelling is typically performed using a description language, such as Verilog or VHDL. For example, the RTL modelling is performed using elementary logic circuits (such as AND logic gates, OR logic gates, multiplexers . . . ) and sequential circuits (such as flip-flops . . . ) provided by a standard cell library. At this point of the process, the exact position of each element is not yet specified; the circuit is only represented as a list of elements required to implement the desired circuit functionality.
Then, a high-level synthesis (or algorithmic synthesis) of the circuit behaviour is performed, in order to simulate the time-dependent behaviour of the RTL model.
During a step of logic synthesis, or logic design, the circuit is implemented at a logic gate level, and described by a gate netlist. This gate netlist is generated from the RTL model and from a design library. Such design libraries usually include hundreds of logic circuit elements. Design libraries depend on the technology used for the fabrication process (such as the technology node, foundry-specific design rules . . . ).
The gate netlist outputted by the logic design is generally a computer file describing an instantiation of the logic gates of the circuit as well as their respective interconnections. This gate netlist may be described in a description language such as Verilog, VHDL or EDIF.
The logic design is followed by a step of placement and routing, or place-and-route. During this place-and-route step, the elements of the previously-defined gate netlist are automatically placed and connected, depending on the user specifications.
The logic design of UTBOX FDSOI circuits typically relies on commercially available EDA tools. As it is desirable to minimize the disruption of established EDA design flows and to avoid any extensive rewriting of existing EDA software, some steps of the design process may reuse elements initially defined for bulk technology. For example, the place-and-route step for UTBOX FDSOI circuits often reuses standard cell libraries containing bulk-technology elements. Additional automated transformations must then be performed, after said place-and-route step, in order to obtain a UTBOX FDSOI-compliant circuit layout.
However, said logic design may also be performed using a dedicated standard cell library containing UTBOX FDSOI-specific elements.
UTBOX FDSOI standard cells often include a nMOS transistor and a pMOS transistor, both formed in the thin silicon layer. This thin silicon layer lies onto the buried insulating oxide layer. The thickness of this oxide layer is typically smaller than 50 nanometers. A semiconductor ground plane, or back-gate, is established under each pMOS and nMOS, below the oxide layer. Each of these ground planes is electrically biased through a semiconductor well. The semiconductor well of each pMOS or nMOS transistor lies below the respective semiconductor ground plane belonging to said transistor, under a deep insulation trench. The threshold voltage of the transistors is adjusted by applying, among other parameters, an appropriate voltage on the respective semiconductor wells. In order to increase the possible combinations of threshold voltage ranges, the ground plane may be doped with either p-type or n-type impurities, for either the pMOS or the nMOS transistors.
In a first configuration, the ground planes of pMOS transistors are electrically biased through an n-doped well; the ground planes of nMOS transistors are electrically biased through a p-doped well. This configuration will henceforth be named regular.
Additionally, while the wells of pMOS transistors are usually biased at an electrical potential Vdd and the wells of nMOS transistors are usually biased at an electrical potential GND, said electrical potentials may be modulated in order to adjust the threshold voltages of said transistors. For example, a forward back biasing (FBB) scheme is commonly used. FBB includes applying a GND+ΔV electrical potential on the wells of nMOS transistors, and a Vdd−ΔV electrical potential on the wells of pMOS transistors. The value of ΔV is chosen smaller than Vdd/2, to avoid the formation of an undesirable forward bias between the n-doped and the p-doped wells of the respective pMOS and nMOS transistors. This forward bias would lead to a leakage current between said wells, which would have adverse consequences on the electrical properties of the circuit.
To remove this limitation on the value of ΔV, it is known to switch the doping type of the wells of pMOS and nMOS transistors. In that configuration, henceforth named flipped, pMOS transistors have a p-doped well, and nMOS transistors have a n-doped well. With this configuration, a different biasing scheme can be used.
In order to increase the performance of the circuit and get the benefits of both flipped and regular configurations, it has been proposed to co-integrate regular and flipped standard cells on a same circuit. This co-integration allows multiple ranges of threshold voltage for the transistors of said circuit, thus leading to a better flexibility of operation.
However, circuits comprising both cells of regular and flipped configurations may have electrical and design-related issues. The abrupt discontinuity between the respective n-doped and p-doped wells of two contiguous regular and flipped standard cells gives rise to so-called singularity points, which may not satisfy design rule checking steps of the design process and may cause mask design problems. This discontinuity may also prevent an adequate electrical biasing of the semiconductor wells. These design issues may affect the reliability of the circuit fabrication process.